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Incorrect output when the order of Phi instructions changes #24

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opened 2025-08-26 18:19:24 +00:00 by ed · 5 comments

ed commented

2025-08-26 18:19:24 +00:00

Owner

This writes "012340" instead of "012345":

import io

main() {
	a := 1
	b := 2
	c := 3
	d := 4
	e := 5
	f := 6

	if true {
		a -= 1
		b -= 1
		c -= 1
		d -= 1
		e -= 1
		f -= 1
	}

	io.write(a)
	io.write(b)
	io.write(c)
	io.write(d)
	io.write(e)
	io.write(f)
}

The output is correct when the if statement does not exist and Phi instructions aren't generated.

This writes "012340" instead of "012345": ``` import io main() { a := 1 b := 2 c := 3 d := 4 e := 5 f := 6 if true { a -= 1 b -= 1 c -= 1 d -= 1 e -= 1 f -= 1 } io.write(a) io.write(b) io.write(c) io.write(d) io.write(e) io.write(f) } ``` The output is correct when the if statement does not exist and Phi instructions aren't generated.

ed added the

bug

label

2025-08-26 18:19:24 +00:00

ed self-assigned this

2025-08-26 18:19:24 +00:00

ed changed title from ~~Incorrect register values with 6 simultaneous Phi instructions~~ to Incorrect output when the order of Phi instructions changes

2025-08-27 12:27:43 +00:00

ed commented

2025-08-27 12:29:38 +00:00

Author

Owner

Minimal example:

import io

main() {
	a := 1
	b := 2

	if true {
		a -= 1
		b -= 1
	}

	io.write(a)
	io.write(b)
}

Expected: 01
Encountered: 01 or 00 depending on the phi insertion order.

Minimal example: ``` import io main() { a := 1 b := 2 if true { a -= 1 b -= 1 } io.write(a) io.write(b) } ``` Expected: `01` Encountered: `01` or `00` depending on the phi insertion order.

ed commented

2025-08-27 12:52:52 +00:00

Author

Owner

The root cause is destination and operand registers being equal for sub.
This is only supported on arm64 but impossible on x86-64.

The root cause is destination and operand registers being equal for `sub`. This is only supported on arm64 but impossible on x86-64.

ed commented

2025-08-27 16:29:33 +00:00

Author

Owner

Partially fixed in cli/q@c53418bbdf.
The remaining work is to reorder the phi moves in such a way that registers don't overlap.

Partially fixed in https://git.urbach.dev/cli/q/commit/c53418bbdf328b5ba4f00bb9bd9f5936feaf5fdc. The remaining work is to reorder the phi moves in such a way that registers don't overlap.

ed commented

2025-08-28 10:04:38 +00:00

Author

Owner

Another partial fix in cli/q@8b5e4d9c82.
Now the live values of all phis need to be equalized.

Another partial fix in https://git.urbach.dev/cli/q/commit/8b5e4d9c824d4ce80446e124b2656da2306e2959. Now the live values of all phis need to be equalized.

ed commented

2025-08-28 12:20:17 +00:00

Author

Owner

Fixed in cli/q@47994041be.

Fixed in https://git.urbach.dev/cli/q/commit/47994041bead85a92d540f4063e95f96b83ccfb0.

ed closed this issue

2025-08-28 12:20:17 +00:00

ed added spent time

2025-08-29 07:45:42 +00:00

16 hours