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Improved division

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This commit is contained in:
Eduard Urbach 2024-08-04 00:35:33 +02:00
parent 745df4df2a
commit f2858b1dc2
Signed by: eduard
GPG key ID: 49226B848C78F6C8
3 changed files with 36 additions and 60 deletions
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32
src/build/asm/Finalize.go
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@ -58,7 +58,34 @@ func (a Assembler) Finalize() ([]byte, []byte) {
}
case DIV:
code = divide(code, x.Data)
switch operands := x.Data.(type) {
case *RegisterRegister:
if operands.Destination != x64.RAX {
code = x64.MoveRegisterRegister(code, x64.RAX, operands.Destination)
}
code = x64.ExtendRAXToRDX(code)
code = x64.DivRegister(code, operands.Source)
if operands.Destination != x64.RAX {
code = x64.MoveRegisterRegister(code, operands.Destination, x64.RAX)
}
}
case MODULO:
switch operands := x.Data.(type) {
case *RegisterRegister:
if operands.Destination != x64.RAX {
code = x64.MoveRegisterRegister(code, x64.RAX, operands.Destination)
}
code = x64.ExtendRAXToRDX(code)
code = x64.DivRegister(code, operands.Source)
if operands.Destination != x64.RDX {
code = x64.MoveRegisterRegister(code, operands.Destination, x64.RDX)
}
}
case CALL:
code = x64.Call(code, 0x00_00_00_00)
@ -144,9 +171,6 @@ func (a Assembler) Finalize() ([]byte, []byte) {
code = x64.LoadRegister(code, operands.Register, operands.Address.Offset, operands.Address.Length, operands.Address.Base)
}
case MODULO:
code = modulo(code, x.Data)
case MOVE:
switch operands := x.Data.(type) {
case *RegisterNumber: