Fixed missing register move in if statements
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parent
646dafd216
commit
cb6b3a4cd0
5 changed files with 63 additions and 14 deletions
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@ -4,18 +4,14 @@ import sys
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sleep(nanoseconds Int) {
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seconds := 0
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loop {
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if nanoseconds >= 1000000000 {
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nanoseconds = nanoseconds - 1000000000
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seconds += 1
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} else {
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timespec := mem.alloc(16)
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store(timespec, 8, seconds)
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offset := timespec + 8
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store(offset, 8, nanoseconds)
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sys.nanosleep(timespec)
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mem.free(timespec, 16)
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return
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}
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if nanoseconds >= 1000000000 {
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seconds, nanoseconds = nanoseconds / 1000000000
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}
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timespec := mem.alloc(16)
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store(timespec, 8, seconds)
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offset := timespec + 8
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store(offset, 8, nanoseconds)
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sys.nanosleep(timespec)
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mem.free(timespec, 16)
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}
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