Fixed incorrect division results

This commit is contained in:
2025-02-22 12:54:23 +01:00
parent 7598411c8f
commit c088697446
11 changed files with 150 additions and 94 deletions

View File

@ -25,7 +25,10 @@ func (f *Function) ExecuteRegisterRegister(operation token.Token, register cpu.R
f.RegisterRegister(asm.MUL, register, operand)
case token.Div, token.DivAssign:
f.SaveRegister(x86.RAX)
if register != x86.RAX {
f.SaveRegister(x86.RAX)
}
f.SaveRegister(x86.RDX)
f.RegisterRegister(asm.DIV, register, operand)