Implemented more arm64 instructions

This commit is contained in:
2025-03-13 23:12:15 +01:00
parent 5b3769a0db
commit ac14ab4f7a
18 changed files with 218 additions and 29 deletions

View File

@ -105,7 +105,8 @@ func (c *compiler) compileARM(x asm.Instruction) {
operand := c.assembler.Param.RegisterNumber[x.Index]
c.append(arm.AddRegisterNumber(operand.Register, operand.Register, operand.Number))
case asm.TypeRegisterRegister:
panic("not implemented")
operand := c.assembler.Param.RegisterRegister[x.Index]
c.append(arm.AddRegisterRegister(operand.Destination, operand.Destination, operand.Source))
}
case asm.SUB:
@ -114,7 +115,8 @@ func (c *compiler) compileARM(x asm.Instruction) {
operand := c.assembler.Param.RegisterNumber[x.Index]
c.append(arm.SubRegisterNumber(operand.Register, operand.Register, operand.Number))
case asm.TypeRegisterRegister:
panic("not implemented")
operand := c.assembler.Param.RegisterRegister[x.Index]
c.append(arm.SubRegisterRegister(operand.Destination, operand.Destination, operand.Source))
}
case asm.COMPARE:
@ -123,6 +125,36 @@ func (c *compiler) compileARM(x asm.Instruction) {
operand := c.assembler.Param.RegisterNumber[x.Index]
c.append(arm.CompareRegisterNumber(operand.Register, operand.Number))
case asm.TypeRegisterRegister:
operand := c.assembler.Param.RegisterRegister[x.Index]
c.append(arm.CompareRegisterRegister(operand.Destination, operand.Source))
}
case asm.DIV:
switch x.Type {
case asm.TypeRegisterRegister:
operand := c.assembler.Param.RegisterRegister[x.Index]
c.append(arm.DivSigned(operand.Destination, operand.Destination, operand.Source))
case asm.TypeRegisterNumber:
panic("not implemented")
}
case asm.MUL:
switch x.Type {
case asm.TypeRegisterRegister:
operand := c.assembler.Param.RegisterRegister[x.Index]
c.append(arm.MulRegisterRegister(operand.Destination, operand.Destination, operand.Source))
case asm.TypeRegisterNumber:
panic("not implemented")
}
case asm.MODULO:
switch x.Type {
case asm.TypeRegisterRegister:
operand := c.assembler.Param.RegisterRegister[x.Index]
quotient := arm.X28
c.append(arm.DivSigned(quotient, operand.Destination, operand.Source))
c.append(arm.MultiplySubtract(operand.Destination, quotient, operand.Source, operand.Destination))
case asm.TypeRegisterNumber:
panic("not implemented")
}