Simplified register names

This commit is contained in:
2025-04-17 14:16:00 +02:00
parent df725a2b23
commit a023b058f8
33 changed files with 922 additions and 930 deletions

View File

@ -44,20 +44,16 @@ const (
)
var (
GeneralRegisters = []cpu.Register{X9, X10, X11, X12, X13, X14, X15, X16, X17, X19, X20, X21, X22, X23, X24, X25, X26}
InputRegisters = []cpu.Register{X0, X1, X2, X3, X4, X5}
OutputRegisters = InputRegisters
SyscallInputRegisters = []cpu.Register{X8, X0, X1, X2, X3, X4, X5}
SyscallOutputRegisters = []cpu.Register{X0, X1}
WindowsInputRegisters = []cpu.Register{X0, X1, X2, X3, X4, X5, X6, X7}
WindowsOutputRegisters = []cpu.Register{X0, X1}
CPU = cpu.CPU{
General: GeneralRegisters,
General: []cpu.Register{X9, X10, X11, X12, X13, X14, X15, X16, X17, X19, X20, X21, X22, X23, X24, X25, X26},
Input: InputRegisters,
Output: OutputRegisters,
SyscallInput: SyscallInputRegisters,
SyscallOutput: SyscallOutputRegisters,
Output: InputRegisters,
SyscallInput: []cpu.Register{X8, X0, X1, X2, X3, X4, X5},
SyscallOutput: []cpu.Register{X0, X1},
NumRegisters: 32,
}
)