cli/q
Code Issues 1 Pull Requests Activity

Simplified register names

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This commit is contained in:
Eduard Urbach
2025-04-17 14:16:00 +02:00
parent df725a2b23
commit a023b058f8
33 changed files with 922 additions and 930 deletions
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12
src/arm/Registers.go
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@ -44,20 +44,16 @@ const (
)
var (
GeneralRegisters = []cpu.Register{X9, X10, X11, X12, X13, X14, X15, X16, X17, X19, X20, X21, X22, X23, X24, X25, X26}
InputRegisters = []cpu.Register{X0, X1, X2, X3, X4, X5}
OutputRegisters = InputRegisters
SyscallInputRegisters = []cpu.Register{X8, X0, X1, X2, X3, X4, X5}
SyscallOutputRegisters = []cpu.Register{X0, X1}
WindowsInputRegisters = []cpu.Register{X0, X1, X2, X3, X4, X5, X6, X7}
WindowsOutputRegisters = []cpu.Register{X0, X1}
CPU = cpu.CPU{
General: GeneralRegisters,
General: []cpu.Register{X9, X10, X11, X12, X13, X14, X15, X16, X17, X19, X20, X21, X22, X23, X24, X25, X26},
Input: InputRegisters,
Output: OutputRegisters,
SyscallInput: SyscallInputRegisters,
SyscallOutput: SyscallOutputRegisters,
Output: InputRegisters,
SyscallInput: []cpu.Register{X8, X0, X1, X2, X3, X4, X5},
SyscallOutput: []cpu.Register{X0, X1},
NumRegisters: 32,
}
)

2
src/arm/Registers_test.go
View File

@ -8,5 +8,5 @@ import (
)
func TestRegisters(t *testing.T) {
assert.NotNil(t, arm.SyscallInputRegisters)
assert.NotContains(t, arm.CPU.General, arm.SP)
}