cli/q
Code Issues 1 Pull Requests Activity

Implemented division by immediates in the IR

Browse Source
This commit is contained in:
Eduard Urbach
2025-03-31 15:51:04 +02:00
parent 008f097186
commit 9302eaef2f
7 changed files with 61 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
src/arm/Registers.go
View File

@ -38,12 +38,13 @@ const (
)
const (
ZR = SP // Zero register uses the same numerical value as SP
TMP = X28 // Temporary register for the assembler
ZR = SP // Zero register uses the same numerical value as SP
TMP = X27 // Temporary register for the assembler
TMP2 = X28 // Temporary register for the assembler
)
var (
GeneralRegisters = []cpu.Register{X9, X10, X11, X12, X13, X14, X15, X16, X17, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28}
GeneralRegisters = []cpu.Register{X9, X10, X11, X12, X13, X14, X15, X16, X17, X19, X20, X21, X22, X23, X24, X25, X26}
InputRegisters = []cpu.Register{X0, X1, X2, X3, X4, X5}
OutputRegisters = InputRegisters
SyscallInputRegisters = []cpu.Register{X8, X0, X1, X2, X3, X4, X5}