Added sum test
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This commit is contained in:
Eduard Urbach 2025-07-04 11:36:26 +02:00
parent 36f76170f5
commit 7a8cb43e9f
Signed by: akyoto
GPG key ID: 49226B848C78F6C8
6 changed files with 66 additions and 6 deletions

View file

@ -4,6 +4,12 @@ import "git.urbach.dev/cli/q/src/cpu"
type Instruction interface{} type Instruction interface{}
type AddRegisterRegister struct {
Destination cpu.Register
Source cpu.Register
Operand cpu.Register
}
type AndRegisterNumber struct { type AndRegisterNumber struct {
Destination cpu.Register Destination cpu.Register
Source cpu.Register Source cpu.Register

View file

@ -16,6 +16,8 @@ func (c *compiler) append(code uint32) {
func (c *compilerARM) Compile(instr Instruction) { func (c *compilerARM) Compile(instr Instruction) {
switch instr := instr.(type) { switch instr := instr.(type) {
case *AddRegisterRegister:
c.append(arm.AddRegisterRegister(instr.Destination, instr.Source, instr.Operand))
case *Call: case *Call:
start := len(c.code) start := len(c.code)
c.append(arm.Call(0)) c.append(arm.Call(0))

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@ -14,18 +14,18 @@ type compilerX86 struct {
func (c *compilerX86) Compile(instr Instruction) { func (c *compilerX86) Compile(instr Instruction) {
switch instr := instr.(type) { switch instr := instr.(type) {
case *AddRegisterRegister:
if instr.Destination != instr.Source {
c.code = x86.MoveRegisterRegister(c.code, instr.Destination, instr.Source)
}
c.code = x86.AddRegisterRegister(c.code, instr.Destination, instr.Operand)
case *AndRegisterNumber: case *AndRegisterNumber:
if instr.Destination != instr.Source { if instr.Destination != instr.Source {
c.code = x86.MoveRegisterRegister(c.code, instr.Destination, instr.Source) c.code = x86.MoveRegisterRegister(c.code, instr.Destination, instr.Source)
} }
c.code = x86.AndRegisterNumber(c.code, instr.Destination, instr.Number) c.code = x86.AndRegisterNumber(c.code, instr.Destination, instr.Number)
case *SubRegisterNumber:
if instr.Destination != instr.Source {
c.code = x86.MoveRegisterRegister(c.code, instr.Destination, instr.Source)
}
c.code = x86.SubRegisterNumber(c.code, instr.Destination, instr.Number)
case *Call: case *Call:
c.code = x86.Call(c.code, 0) c.code = x86.Call(c.code, 0)
end := len(c.code) end := len(c.code)
@ -102,6 +102,12 @@ func (c *compilerX86) Compile(instr Instruction) {
c.code = x86.MoveRegisterRegister(c.code, instr.Destination, instr.Source) c.code = x86.MoveRegisterRegister(c.code, instr.Destination, instr.Source)
case *Return: case *Return:
c.code = x86.Return(c.code) c.code = x86.Return(c.code)
case *SubRegisterNumber:
if instr.Destination != instr.Source {
c.code = x86.MoveRegisterRegister(c.code, instr.Destination, instr.Source)
}
c.code = x86.SubRegisterNumber(c.code, instr.Destination, instr.Number)
case *Syscall: case *Syscall:
c.code = x86.Syscall(c.code) c.code = x86.Syscall(c.code)
default: default:

View file

@ -211,6 +211,32 @@ func (f *Function) Evaluate(expr *expression.Expression) (ssa.Value, error) {
return nil, errors.New(&UnknownIdentifier{Name: label}, f.File, left.Token.Position) return nil, errors.New(&UnknownIdentifier{Name: label}, f.File, left.Token.Position)
default: default:
if expr.Token.IsOperator() {
left := expr.Children[0]
right := expr.Children[1]
leftValue, err := f.Evaluate(left)
if err != nil {
return nil, err
}
rightValue, err := f.Evaluate(right)
if err != nil {
return nil, err
}
v := f.Append(&ssa.BinaryOp{
Left: leftValue,
Right: rightValue,
Op: expr.Token.Kind,
Source: ssa.Source(expr.Source),
})
return v, nil
}
panic("not implemented") panic("not implemented")
} }
} }

View file

@ -12,6 +12,16 @@ import (
// ValueToRegister moves a value into the given `destination` register. // ValueToRegister moves a value into the given `destination` register.
func (f *Compiler) ValueToRegister(instr ssa.Value, destination cpu.Register) { func (f *Compiler) ValueToRegister(instr ssa.Value, destination cpu.Register) {
switch instr := instr.(type) { switch instr := instr.(type) {
case *ssa.BinaryOp:
f.ValueToRegister(instr.Left, destination)
f.ValueToRegister(instr.Right, 7)
f.Assembler.Append(&asm.AddRegisterRegister{
Destination: destination,
Source: destination,
Operand: 7,
})
case *ssa.Bytes: case *ssa.Bytes:
f.Count.Data++ f.Count.Data++
label := f.CreateLabel("data", f.Count.Data) label := f.CreateLabel("data", f.Count.Data)

10
tests/sum.q Normal file
View file

@ -0,0 +1,10 @@
main() {
t1 := sum(1, 2)
t2 := sum(3, 4)
t3 := sum(t1, t2)
syscall(60, t3)
}
sum(a int, b int) -> int {
return a + b
}