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Implemented simple expressions

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This commit is contained in:
Eduard Urbach 2024-06-25 20:50:06 +02:00
parent c437b1d0f8
commit 37e222e022
Signed by: eduard
GPG key ID: 49226B848C78F6C8
12 changed files with 232 additions and 52 deletions
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16
src/build/asm/Assembler.go
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@ -31,18 +31,24 @@ func (a *Assembler) Finalize() ([]byte, []byte) {
switch operands := x.Data.(type) {
case *RegisterNumber:
code = x64.AddRegNum(code, operands.Register, operands.Number)
case *RegisterRegister:
code = x64.AddRegReg(code, operands.Destination, operands.Source)
}
case SUB:
switch operands := x.Data.(type) {
case *RegisterNumber:
code = x64.SubRegNum(code, operands.Register, operands.Number)
case *RegisterRegister:
code = x64.SubRegReg(code, operands.Destination, operands.Source)
}
case MUL:
switch operands := x.Data.(type) {
case *RegisterNumber:
code = x64.MulRegNum(code, operands.Register, operands.Number)
case *RegisterRegister:
code = x64.MulRegReg(code, operands.Destination, operands.Source)
}
case DIV:
@ -65,6 +71,16 @@ func (a *Assembler) Finalize() ([]byte, []byte) {
code = x64.PopReg(code, x64.RDX)
code = x64.PopReg(code, x64.RAX)
}
case *RegisterRegister:
code = x64.PushReg(code, x64.RAX)
code = x64.PushReg(code, x64.RDX)
code = x64.MoveRegReg64(code, x64.RAX, operands.Destination)
code = x64.ExtendRAXToRDX(code)
code = x64.DivReg(code, operands.Source)
code = x64.MoveRegReg64(code, operands.Destination, x64.RAX)
code = x64.PopReg(code, x64.RDX)
code = x64.PopReg(code, x64.RAX)
}
case CALL:

11
src/build/asm/Instructions.go
View file

@ -13,6 +13,17 @@ func (a *Assembler) RegisterNumber(mnemonic Mnemonic, reg cpu.Register, number i
})
}
// RegisterRegister adds an instruction using two registers.
func (a *Assembler) RegisterRegister(mnemonic Mnemonic, left cpu.Register, right cpu.Register) {
a.Instructions = append(a.Instructions, Instruction{
Mnemonic: mnemonic,
Data: &RegisterRegister{
Destination: left,
Source: right,
},
})
}
// MoveRegisterRegister moves a register value into another register.
func (a *Assembler) MoveRegisterRegister(destination cpu.Register, source cpu.Register) {
a.Instructions = append(a.Instructions, Instruction{