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Added more RISC-V registers

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This commit is contained in:
Eduard Urbach 2024-08-18 09:52:45 +02:00
parent 3eba9fb526
commit 201f783a4d
Signed by: eduard
GPG key ID: 49226B848C78F6C8
1 changed files with 4 additions and 1 deletions
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5
src/arch/riscv/Registers.go
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@ -37,4 +37,7 @@ const (
X31
)
var SyscallInputRegisters = []cpu.Register{X10, X11, X12, X13, X14, X15, X16}
var (
SyscallInputRegisters = []cpu.Register{X17, X10, X11, X12, X13, X14, X15, X16}
SyscallOutputRegisters = []cpu.Register{X10, X11}
)